This article will introduce the Advanced Microcontroller Bus Architecture (AMBA), an open standard for SoC designs.
As semiconductor manufacturing has evolved, the ability to install more logic gates in the same matrix size has steadily increased. The fact of being able to include more and more components on the same chip led to the birth of the SoC or system on a chip.
An SoC is typically defined as an integrated circuit that includes all the necessary elements that make up a computer. This includes the CPU, RAM, non-volatile storage, a UART, and any other peripherals the system needs. With a large number of different components on the same chip, efficient connection and management of these subsystems quickly became a challenge.
The Advanced Microcontroller Bus Architecture (AMBA) is an attempt to solve this problem.
What is AMBA?
AMBA is an open standard that describes how to connect and manage the different components or blocks within an SoC. The AMBA specification was developed by ARM and has become the de facto standard for interconnecting components in an SoC. While AMBA is currently in its 5th revision has evolved significantly over time, legacy implementations are widely used and remain relevant. With this in mind, this article will use Revision 2.0 as a starting point and build on these ideas in a future article.
The AMBA specification was developed to solve some key problems in SoC design. One of them is development correct for the first time, which means that if used correctly, AMBA can ensure a consistent design from the beginning, reducing costly redesigns. Another key requirement of AMBA was technological independence or making the designs reusable and oblivious to the specifics of the system components. With the modular system design, AMBA encourages the development of component libraries so that work done once does not need to be repeated. A final motivation for AMBA was to minimize the amount of silicon that was needed for both on-chip and off-chip communications.
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Three different buses are described in Revision 2.0 to facilitate on-chip communications. These are the Advanced High Performance Bus (AHB), the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The AHB is the backbone of the system and is specifically designed for high-performance, high-frequency components. This includes connections for processors, memory on chips, and memory interfaces, among others.
The ASB is an alternative to the AHB where some high performance features are not needed. The APB is a simplified interface designed for low-bandwidth peripherals that do not require the high performance of the AHB or ASB. These include components like a UART, low frequency GPIO, and timers.
Figure 1. AMBA bus including AHB / ASB and APB (taken from AMBA Rev. 2.0)
Advanced high-performance bus
The AHB was a new addition to AMBA in revision 2.0. Added to accommodate high-performance designs. Some of the new features added were split transactions, single cycle bus master handover, single clock edge operation, and more extensive data bus configurations, ie 64/128 bits.
An AHB must contain a number of components outside of the masters and slaves. These components are an address and control multiplexer, a read multiplexer, a write multiplexer, a decoder, and an arbiter. Figure 2 shows three masters connected to four slaves in an AHB. The signals displayed are the address signal (HADDR), the write data bus (HWDATA), and the read data bus (HRDATA). The address is used for slave selection, the write data bus is used to move data from master to slave, and the read data bus is used to move data between slave and master.
Figure 2. AHB with masters, slaves, muxes, referee and decoder (AMBA Rev. 2.0)
When a teacher needs to take control of the bus, they must first send a request to the referee.
The arbitrator grants access based on a prioritization scheme that ensures that teachers with a higher priority receive access first. This prioritization scheme is not defined by AMBA and will differ between designs. Various control signals are used to define the direction, width, and type of data transfer. The AHB decoder receives the address signal from the master and decodes it into slave select signals. The slave responds to the master via an HRESP signal and begins data transfer between the master and the slave.
In total, there are about 20 different AHB signals, each with a unique purpose. Figure 3 shows the AHB signals along with the ASB signals for reference.
Advanced bus system
The ASB is a simplified version of the AHB and offers high performance for 16-bit and 32-bit systems. Many of the same signals in an AHB are used for the ASB, apart from certain control signals that allow split transactions.
The operation of the ASB begins with a master requesting access to the bus from the referee. The arbitrator grants the request and the transfer begins. The decoder decodes the address placed on the bus and selects a slave. The slave responds to the master and the data transfer takes place.
Figure 3. AHB signals compared to ASB signals
Advanced Peripheral Bus
The APB is a simplified interface for low-frequency system components. Revision 2 further simplified the bus by having all signal transitions synchronized with the rising edge of the clock.
The APB consists of a single master bus called the APB bridge, which acts as a slave on the AHB / ASB. Therefore, the bridge is the interface between the high-performance bus and the low-frequency peripherals. The peripheral devices on the APB are the slaves. Figure 4 lists the names of the APB signals.
Figure 4. APB signals
Figure 5 below shows an example AMBA system running with two AHB masters, one AHB slave, and two APB slaves. Also note the AHB arbiter, AHB decoder, and APB bridge.
Figure 5. Example of an AMBA system. Click to enlarge.
The APB bridge has an AHB slave interface, so it looks like another slave from the masters. This system has been simplified with some minor signals and items (such as reset signals and multiplexers) removed. Output signals come out of the right side of a block and input signals come in on the left side of a block. Input signals are also denoted by an arrowhead. Thicker lines represent larger data paths.
This system is writing to one of the APB slaves over the course of approximately seven clock cycles. The AHB is a segmented bus and has dedicated read and write paths, so a read could occur in the middle of this write. For more accurate time information, see the AMBA 2.0 standard revision.
AXI – Looking to the future
Eventually the AHBs reached the limits of performance and by 2003 ARM had released a new generation of AMBA protocols. AMBA revision 3.0 introduced the AXI protocol. AXI stands for Advanced Extensible Interface and offers even higher performance than AHB, implemented through a point-to-point connection scheme. Instead of a system bus, the AXI interconnect allows transactions between masters and slaves using only a few well-defined interfaces.
In the following AMBA article, we will discuss AXI3 and AXI4 and how they are used to interconnect SoC components.
Figure 6. AXI Interconnect (AXI4 Specification)
In this article, we introduce the Advanced Microcontroller Bus Architecture or AMBA. AMBA is an open standard that describes how the components of an SoC can exchange data quickly and efficiently.
AMBA has become a de facto standard and is currently in its fifth revision. Starting with revision 2.0, we look at AHB, ASB, and APB and how they work from a high level. While many of these bus protocols have been superseded by future AMBA revisions, they are still relevant in legacy designs and as a basis for future learning.
Whether you are interested in SoC design professionally or as a hobby, AMBA is a crucial step on your journey.